(a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to the structure of a programming circuit in the nonvolatile semiconductor memory device.
(b) Description of the Related Art
Flash memory is known as a typical nonvolatile semiconductor memory device, wherein each memory cell includes a MOSFET having a floating gate for programming of the memory cell.
FIG. 1 shows a conventional flash memory, which includes a programming section 201, a memory cell array 203 and a selector section 202. The programming section 201 includes voltage divider 210 including resistors R21 and R22 for dividing source potential VPP, an n-channel undoped MOSFET (nMOSFET) Tr21 having a gate coupled to an output node of the voltage divider 210. The memory cell array 203 includes a plurality of memory cells arranged in a matrix and each implemented by a single cell transistor Tr26 . . . Tr29. The cell transistor Tr26 . . . Tr29 has a source connected to the ground, a drain connected to a corresponding bit line B21 . . . B24 extending in the column direction, and a gate connected to a corresponding word line W2 extending in the row direction. The selector section 202 includes a plurality of p-channel MOSFETs (pMOSFETs) Tr22 to Tr25 each corresponding to a bit line B21 . . . B24 for selection thereof.
The potential of node C2 connecting the resistors R1 and R2 together is applied as a reference potential to the gate of nMOSFET Tr21, which delivers a programming voltage from the source through node A2. Since the undoped nMOSFET Tr21 has a threshold voltage of zero volt, the potential of node A2 is substantially equal to the reference potential at node C2.
In a programming operation of a cell transistor Tr26, for example, a high voltage is applied to the word line W2, and the gate potential Y21 of pMOSFET Tr22 is set below the potential of node A2 minus the absolute value of the threshold voltage VTP2 of pMOSFET Tr22 to turn on the pMOSFET Tr22, whereby the drain of the cell transistor Tr26 is applied with the programming voltage. Thus, cell transistor Tr26 is turned on to pass the drain current, whereby hot electrons are generated in the vicinity of the drain of the cell transistor Tr26 to be injected into the floating gate of the cell transistor Tr26 for programming. At this stage, although the potential of node A2 is lowered by a product of the on-resistance of the undoped nMOSFET Tr21 and the drain current of the cell transistor Tr26, the potential of node A2 resides substantially at the specified setting voltage due to the small on-resistance of the undoped nMOSFET Tr21, whereby a desired programming speed is obtained.
Assuming that the undoped nMOSFET Tr21 operates in a saturated state, the drain current Ids thereof is expressed by: EQU Ids=(1/2).beta.(W/L)Vgs.sup.2.
wherein .beta., W, L and Vgs are a constant, gate width, gate length and the source-to-gate voltage of the undoped nMOSFET. The drain current Ids is set at a maximum programming current and .beta. is determined by the fabrication process. The potential of node A2 is determined as the desired programming voltage for programming the cell transistors. Since the source-to-gate voltage Vgs is equal to the potential of node C2 minus the potential of node A2, the ratio of W/L for the undoped nMOSFET Tr21 can be determined based on the maximum drain current or the maximum programming current.
On the other hand, in a programming operation for a row or group of the cell transistors Tr26 to Tr29 at a time, the potential of word line W2 is set at a high voltage, the potentials Y21 to Y24 of the gates of pMOSFETs Tr22 to Tr25 are set below the potential of node A2 minus the absolute value of the threshold voltage VTP2 of pMOSFETs Tr22 to Tr25 to turn on the pMOSFETs Tr22 to Tr25, whereby the drains of the cell transistors Tr26 to Tr29 are applied with the programming voltage.
Thus, cell transistors Tr26 to Tr29 are turned on to pass the drain currents, whereby hot electrons are generated in the vicinities of the drains of the cell transistors Tr26 to Tr29 to be injected into the floating gates of the cell transistors Tr26 to Tr29 for programming.
FIG. 2 shows the potential of node A2 at this stage as well as the potentials of other nodes. The potential of node A2 is lowered by a product of the on-resistance of undoped nMOSFET Tr21 and the sum IWO of the drain currents of the cell transistors Tr26 to Tr29. The reduction of the potential of node A2 by Vgs with respect to the potential of node C2 causes that the programming voltage is lower than the critical voltage WX which allows safe programming of the cell transistor.
More specifically, although the on-resistance of the undoped nMOSFET Tr21 is set at a low value, the potential of node A2 is lowered below the critical voltage due to the drain currents of the cell transistors Tr26 to Tr29. This lowers the programming speed of the cell transistors Tr26 to Tr29 compared to the case of programming of the single cell transistor Tr26. This may be called an inherent problem involved in the output voltage supplied from a source follower scheme.